1. Field of the Invention
This invention relates generally to computer memory, and more particularly to systems and methods for identification of faulty or weak memory cells.
2. Description of the Related Art
In the semiconductor industry, embedded memories have become enormously popular as a critical part of Large Scale and Very Large Scale integrated circuits (ICs). Embedded memories allow custom or semi-custom design of ICs that implement part or whole of a system on a chip (SOC), which helps reduce the total component count and manufacturing costs. These ICs also usually employ libraries of xe2x80x9cstandard cellsxe2x80x9d as building blocks to construct the desired logic circuits. Standard cells include commonlyused logic functions, such as NOR, NAND, INVERT, and further may also include decoders, registers, counters, and other more complex components.
FIG. 1 is a diagram showing a conventional embedded memory used in IC designs 100. The memory core includes a memory array 102 having a plurality of memory bit cells 110. The memory bit cells 110 perform the main function of storing the data in the form of binary logic values of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Further included is x-decode circuitry 104, y-decode circuitry 106, sense amplifier circuitry 109, I/O circuitry 113, and control circuitry 108. The x-decode circuitry 104 and the y-decode circuitry 106 provide the ability to select or access a specific memory cell 110 based on encoded address location provided as input to the embedded memory. The sense amplifier circuitry 109 and the I/O circuitry 113 enable faster access to the selected memory cell 110. The control circuitry 108 controls the function and timing of the decode circuitry 104/106, sense amp circuitry 109, and the I/O circuitry 113 by generating internal timing pulses, buffering external input signals and clocks and defining the action to be performed on the memory bit cell. For example, in case of a RAM the action could be a read or a write.
The memory array 102 is generally organized in a two-dimensional array, wherein the memory cells 110 are addressed at the intersection of rows, or xe2x80x9cword lines,xe2x80x9d and columns, or xe2x80x9cbit lines,xe2x80x9d of the memory array 102. To access a given memory cell 110, it is necessary to select the word line and the bit line at the intersection where the memory element is located. For this purpose, memory addresses are divided into row and column address signals, which are decoded independently using the x-decode circuitry 104 and the y-decode circuitry 106.
The memory core 100 can include single or multiple configurable memory arrays 102 with identical numbers of rows and columns. Embedded memories are typically designed to provide access to multiple cells 110 in a row in parallel during the same cycle, which is typically defined by the primary clock signal input for the memory. In this case, a plurality of column lines can be grouped together to form an I/O (input/output) memory block array whose column lines are multiplexed into a single I/O by dedicated Y-decode 106, Sense Amp 109 and I/O 113 circuits. A Memory I/O block then includes the cell array and corresponding Y-decode, Sense Amp and I/O circuitry that will provide access to one single cell 110 per access cycle. In such instance, the memory array 102 contains rows of memory cells 110 that are accessed by activation of the row word line. Groups of these cells are multiplexed into one output, and each such output is accessed concurrently with all the others during the same cycle. Each intersecting point between a row (word line) and an I/O memory block represents the group of memory cells 110, only one of which is accessed at the I/O pin during a cycle. The collection of these cells in FIG. 1 form a memory macro unit. One or more of such memory units are used as the principle building block for implementing storage elements on a custom or semi-custom IC or SOC chip.
Although IC Manufacturers strive to produce chips with minimum defects, as a practical matter, defects do occur for various reasons. Such causes can happen during the manufacturing process, such as when random particles of dust settle on the surface of a silicon wafer during processing. Embedded memories are increasingly susceptible to such defects as the density and quantity of memory on ICs increases. The impact of defect within the embedded memories on the overall yield, or the ratio of good parts to total parts, has increased significantly. Since a single defect in a single memory cell can render the whole IC or SOC unusable, techniques to repair such defects by use of extra storage cells have been implemented to improve the overall yield and hence reduce the cost of the IC.
The memory core 100 of FIG. 1 shows three faulty or weak memory cells 112. The memory cells 110 that fail to store or retain the correct data altogether are considered faulty or xe2x80x9chardxe2x80x9d errors. The memory cells 110 that fail to present correct data in expected time are considered weak or xe2x80x9csoftxe2x80x9d errors. Weak cells are also memory cells 110 whose performance degrades sufficiently in response to the operating environment such that the memory cells 110 fail to present correct data in expected time.
Such a weak or faulty cell can be caused, for example, by the degradation of the devices, transistors, metal or other bridging defects, defective devices in the cell, or other reasons. Degradation of the devices in the cell can occur from extended use of the memory cell that is coupled with an imperfectly manufactured device. Bridging defects can occur during the semiconductor fabrication process from minor, localized variation in the processing steps like metal deposition or etching. Defective devices in the cell can be the result of undesirable particles that settle onto a semiconductor layer. A single memory cell failure will cause the entire IC or SOC chip to malfunction, and render the chip unusable, unless the defective memory cell can be repaired or replaced to ensure proper functioning of the IC or SOC chip.
Another difficulty arises from packing higher-density building blocks into an IC or SOC chip. Large memory blocks contain a multitude of row memory lines intersecting I/O memory blocks. As a memory array increases in size, the number of correctly functioning memory arrays decreases proportionally, caused by the increasing likelihood of locating memory cell defects within the larger memory array. In order to produce such IC or SOC with large memories while maintaining cost control, some methodology of redundant storage that can be used to repair the defective memories is desirable.
Laser fuse based or other xe2x80x9cwiredxe2x80x9d in repair methods, and built-in self-repair (BISR) methods have been used to repair faulty and weak memory cells via redundant storage elements. Memory cells 112 that prove defective during testing of the memory are replaced by the redundant memory storage elements. Redundancy and repair circuits typically include either laser programmable fuses or other memory elements suitable to store those address configurations that correspond to the defective memory elements and need to be replaced.
Laser programmable fuses have several disadvantages including requiring significant testing and laser programming manufacturing infrastructure. Furthermore, laser programmable fuses are large due to guard ring and other requirements imposed by the laser repair machines. Laser fuse programming does not work correctly 100% of the time, causing additional yield loss. Further, laser programmable fuses must be programmed prior to packaging and therefore all the defects must be identified prior to repair. Identification of the weak cells requires significant additional testing due to their environment dependent nature.
BISR systems use similar approaches. In case of BISR, the circuitry to perform all of the functions is embedded onto the same IC, SOC, or on the same system board, as the memory that may need to be repaired. When these functions are placed outside the IC at the system board level, access to appropriate elements on the IC is provided through pins to perform the repair operation.
A BISR includes a built in self-test (BIST) component that allows testing of the target memories to identify faulty locations. The BISR is typically executed when the IC, SOC, or the system board is first powered up, or upon a top-level reset. During the self test, test patterns are generated by a data generator within the BIST and the data is written to and read from all of the locations in the memory under the control of the BIST. The BIST also has address generators that generate addresses in a way to test all the cells in the memory.
A comparator compares data read from the memory array with data expected from the data generator and, if there is a mismatch, the faulty address is stored into a register in an encoded form. After the entire memory is tested, the BISR circuitry determines if there is sufficient redundant storage available to repair all the faulty locations, and generates a flag signal to indicate that the memory is OK. If the flag indicates failure to repair during the factory testing of the part, the part can be discarded. When the part is qualified, it is put in the system and shipped to customers. Once the part or the system is shipped to the customer, the flag indicating memory is OK is not used. The BISR circuits, on the other hand, continue to perform the self-repair operation every time the system is powered up in the field.
During memory access operations, the faulty addresses stored in the fault register block are used to divert (or redirect) an access to a faulty address to a non-faulty redundant address. A memory access address is compared to the contents of the fault register data and, if a match occurs, the access is redirected to the appropriate redundant address. Redirection is provided by the redundancy control block within BISR that supplies an appropriate redundant address to the embedded memory.
Although BISR provides repair functionality without requiring laser fuses, problems can occur when the memory is used under conditions different than were present during the BISR testing during chip power up or reset. Specifically, the tests performed on the memory core during the BISR process may not adequately cover what can occur once the IC or SOC starts operating in it""s normal mode after BISR, such as when a memory cell is xe2x80x9cweak.xe2x80x9d
A weak memory cell may function properly during BISR testing during chip or system power up or reset, however, when operating conditions change, such as the operating temperature or voltage, a weak memory cell may start failing. It is very common for the temperature of an IC or SOC to increase significantly after the initial power up or reset. Thus, a conventional BIST or BISR can easily detect a memory cell that is faulty because the cell cannot be read or written to during the testing operation.
However, a weak memory may not be detected by a conventional BIST or BISR system because a weak memory cell will function normally during the testing that occurs under the less stressful conditions that usually exist during power up or reset. Unfortunately, if the system having one or more weak memory cells was repaired by the conventional BISR during the power up or reset step, there is a potential for the weak cells to start failing once the operating conditions change, for example, by an increase in the temperature of the IC or the system board. This will cause the entire system to fail as the system is expecting a correctly functioning memory after BISR. Such system failures are usually not acceptable to the users of the system. As a result, the use of BISR to repair embedded memories is severely limited.
In view of the forgoing, there is a need for improved memory testing methods. The methods should reduce the effect of weak memory cell failure after burn-in. Further, the methods should allow simulation of extreme operating conditions without extensive environmental tests including tests under higher than normal voltages and temperatures. This will benefit both testing during production and for BISR operation.
Broadly speaking, the present invention fills these needs by providing a testing system that uses a stress clock signal having a decreased pulse width, which simulates extreme operating conditions and allows detection of both faulty memory cells and weak memory cells. In one embodiment, a method for identifying faulty and weak memory cells is disclosed. A normal internal clock signal for use in accessing a memory array is provided, wherein the memory array may contain redundant memory cells that can be accessed during normal operation. In addition, a test is performed on the memory array using a stress clock signal. Each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. In this manner, memory cells that fail the test using the stress clock signal are identified as non-usable memory cells. In some embodiments, the normal internal clock signal is based on required read and write times for the memory cells of the memory array and a margin added to the required read and write times. The amount of optimal margin can be derived from the expected variations in the required read and write times for the memory cells of the memory array due to possible variations in environmental conditions, operating conditions and other factors. Each pulse of the stress clock signal can be approximately equal to each pulse of the normal internal clock signal minus the margin. Preferably, the stress clock signal is not used during normal memory access operations, while the normal internal clock signal is used during normal memory access operations.
In another embodiment, a method for identifying faulty functional logic is disclosed. Similar to above, an normal clock signal for use in accessing functional logic is provided, where the functional logic has access to redundant functional logic during normal operation. In addition, a test is performed on the functional logic using a stress clock signal, where each pulse of the stress clock signal is of a shorter duration than each pulse of the normal clock signal. In this manner, functional logic elements that fail the test using the stress clock signal are identified as non-usable functional logic elements.
In further embodiment, an embedded memory device is disclosed. The embedded memory device includes a memory array may contain redundant memory cells that can be accessed during normal operation, and a programmable normal internal clock. The programmable normal internal clock can be programmed to generate a stress clock signal, wherein each pulse of the stress clock signal is of a shorter duration than each pulse of a normal normal internal clock signal used in accessing the memory array. Also included in the embedded memory device is a built-in self-test circuit that performs a built-in self-test using the stress clock signal. In this manner, extreme operating conditions are simulated by the stress signal. Optionally, the embedded memory device can include a storage, such as a register, that stores defective memory addresses detected by the built-in self-test circuit. Further, redundant control logic can be included that redirects memory access operations to the defective memory addresses to redundant memory cells.
A method for testing a memory under simulated extreme conditions is disclosed in another embodiment of the present invention. A normal internal clock signal is provided for use in accessing a memory array, wherein the memory array may contain redundant memory cells that can be accessed during normal operation. In addition, the memory array is tested using a stress signal having a pulse width that is shorter than a pulse width of the normal internal clock signal, and memory cells that fail the test using the stress signal are recorded as non-usable memory cells. In this manner, extreme operating conditions are simulated by the stress signal. As above, the normal internal clock signal can be based on required read and write times for memory cells of the memory array, and on a margin added to the required read and write times for memory cells of the memory array. Further, each pulse of the stress clock signal can be approximately equal to each pulse of the normal internal clock signal minus the margin.
Advantageously, the embodiments of the present invention are capable of detecting weak memory cells via the stress clock signal. Further, the embodiments of the present invention can be used to simulate extreme operating conditions that may occur in field use via the stress clock signal. The stress clock signal can mimic the effects of variables such as temperature and voltage. Hence, time can be saved using the embodiments of the present invention since variances in variables such as temperature and voltage can be simulated using the stress clock signal instead of actually altering the individual test variables.
Moreover, the embodiments of the present invention can utilize the stress clock signal to perform a high stress BIST or BISR upon the ASIC memory during power up or reset of the ASIC. In particular, during power up or reset of the ASIC, the BISR system tests the memory core using the stress clock signal, which facilitates discovery of weak memory cells as well as faulty memory cells.